The patent document 1 (JP-A-HEI03-022465) discloses a resin sealing type semiconductor device having a semiconductor element (chip) sealed with resin. In the configuration of this semiconductor device, the semiconductor element is mounted on an island larger in size than the semiconductor element. In this case, both the front surface of the semiconductor element and the back surface of each lead frame disposed on the island are coated with a polyimide-based resin film having a thickness of 5 to 100 μm so as to give favorable adherence to both the sealing resin and the semiconductor element/lead frames and absorb the stress to be generated between the sealing resin and each of the semiconductor element/lead frames.
However, if the surface of the semiconductor element is also coated with a polyimide-based resin film in such a way according to the technique as disclosed in the patent document 1, the manufacturing cost rises. Furthermore, if the island is larger in size than the chip and polyimide-based resin is to be coated all over the back surface of the island, the resin coating will have to be made on a wider area, thereby the manufacturing cost further rises.
In recent years, there have come to be employed semiconductor devices in which the lead frames are disposed in a chip area that is smaller in size than the chip. If the lead frames disposing area on the chip is smaller than the chip in such a way, semiconductor devices will come to be able to correspond to chips in various sizes and mount those chips with use of only one type of lead frames. Furthermore, lead frames can be used commonly among those chips, thereby the lead frame material cost is reduced and accordingly the manufacturing cost of the semiconductor device is reduced. And the coating amount of the mounting material required between the lead frames disposing area on the subject chip and the chip itself is required less, thereby the mounting material and the manufacturing cost can be reduced. These are the merits of those semiconductor devices.
The patent document 2 (JP-A-2005-109007) also discloses a semiconductor device in which a semiconductor chip and its leads are overlapped with each other and part of each lead is positioned under the semiconductor chip. The semiconductor chip is adhered not only to a tab where the chip is mounted, but also to an island provided for the hanging leads connected to the tab with an adhesive material.
On the other hand, the patent document 3 (JP-A-HEI07-321280) discloses a die pad having a cross-shaped chip adhering surface. The chip adhering surface is smaller than the subject chip, so the surrounding surface of the chip is practically exposed when the chip is adhered to the adhering surface.